This invention relates to the field of delay locked loops, and in particular to a novel delay element.
Delay locked loops are used to control the timing of an internal clock signal, to match that of an input or external clock signal. Typically an external clock signal is passed through a delay line, where the external clock signal is delayed for a controllable time. The output signal of the delay line is applied to a circuit to be clocked via a clock distribution tree. One of the clock signals from the distribution tree (the internal clock signal) is applied with the external clock to a comparator, which determines any phase difference. The difference is used to generate delay line control signals, which are applied to the delay line so as to cause the delay to vary and thus minimize any phase difference between the external clock signal and the internal clock signal.
Typically the delay line is formed of coarse delay elements and one or more fine delay elements. One or more coarse delay elements are connected in series with a fine delay element. The fine delay element can be adjusted to the maximum time delay of one coarse delay element. A system which uses this structure is described in U.S. patent application Ser. No. 09/106,755 filed Jun. 30, 1998, and entitled xe2x80x9cProcess, Voltage and Temperature Independent Switched Delay Compensation Schemexe2x80x9d, invented by Gurpreet Bhullar et al, which is incorporated herein by reference.
In delay lines of this type, plural inverters are connected in series between an input for receiving the input clock and an output. Switches controlled by the delay line control are switched so as to bypass various ones of the inverters, and thus control how many inverters the external clock signal has to pass through.
However, it has been found that since even the fine delay is controlled in steps, there is some jitter remaining. This is because in attempting to maintain the DLL setting about a lock point, the DLL control circuitry may attempt to add and remove one fine delay element continuously. If one fine control step does not set the delay to cause the internal clock signal to be exactly in phase with the external clock, there will be jitter about the lock point.
It has also been found that the fine delay line cannot always compensate for one coarse delay element since the coarse element delay can have a longer delay than the maximum that can be provided by the dynamic range of the fine delay control due to temperature and voltage conditions.
It has also been found that noise on the power supply rails can cause jitter in the output signal of the delay line, especially in the case of RC-based inverter delay lines.
The digital delay line also takes up significant integrated circuit area, due to the resistors and capacitors required to provide the digital delay line.
It is also desirable to have as large a dynamic range as possible. This dynamic range is limited in a delay line having fixed coarse and fine delay elements. Furthermore, each delay element of the delay line will experience large variation of delay with variations in temperature and voltage.
The present invention has several advantages over the digital delay line described above. In a comparison between the above described digital delay line, in a prototype which had five delay elements to provide a certain delay variation, only two elements were required using the present invention to achieve approximately the same dynamic range. Thus there is substantial improvement in dynamic range of each element.
The present invention also takes up smaller integrated circuit chip area than the above-described digital delay line, for approximately the same delay, since plural resistors and capacitors are not required.
The dynamic range increases with decreasing frequency in the present invention, which is the opposite of that of the digital delay line, for which more and more elements would be required to make up the increased delay time that would be required in a low frequency device and for test purposes.
The control voltages used in the present invention can be made very accurate and immune to temperature and voltage variations. The delay is thus substantially immune to process variations.
The present invention uses analog delay elements, instead of digital delay elements of the prior art.
In accordance with an embodiment of the present invention, a delay line for receiving an input clock signal and internally delaying the input clock signal to produce an output clock signal, the delay line comprising: a plurality of analog delay elements, each analog delay element having a first delay adjustment input and a second delay adjustment input, a first bias voltage generator for providing a first bias voltage to the first delay adjustment input of each analog delay element, a second bias voltage generator for providing a second bias voltage to the second delay adjustment input of each analog delay element, a delay line control circuit for controlling the first and second voltage bias generators in response to a phase comparison between the output clock signal and the input clock signal, and a third bias voltage generator for providing a third bias voltage as an input to both the first and second bias voltage generators.
In accordance with another embodiment, a method for delaying a clock signal through a delay line having a plurality of delay elements comprising the following steps: receiving a digital input clock signal first edge, generating a first ramp voltage at a first node in response to the presence of the clock signal first edge, the ramp voltage having a slope which is dependent on a current which is controlled by a bias voltage, said bias voltage being generated based on a counter output, generating an output voltage first edge at a second node in response to a comparison between the first ramp voltage and a predetermined voltage level, generating a digital output clock signal first edge in response to the output voltage first edge at the second node, receiving a second edge of the digital input clock signal, and generating a digital output clock signal second edge in response to second edge of the digital input clock.
In accordance with another embodiment, a method of delaying an input clock signal comprising: receiving a digital clock signal, applying the digital clock signal to an analog delay element having both coarse and fine delay control inputs, applying both coarse and fine delay control signals to the respective coarse and fine delay control inputs for controlling an amount of fine and coarse delay through the delay element, said coarse and fine delay control signals being generated based on an output from a coarse delay counter and on an output from a fine delay counter respectively, and outputting a digital clock signal delayed from the input clock signal by an amount equal to the sum of the fine and coarse delays through the delay element.